By Ramesh K Choudhary, Jyotsna Kumar Mandal, Nitin Auluck, H A Nagarajaram
This booklet highlights a set of top of the range peer-reviewed examine papers awarded on the 9th overseas convention on complex Computing & communique applied sciences (ICACCT-2015) held at Asia Pacific Institute of knowledge expertise, Panipat, India in the course of 27–29 November 2015. The publication discusses a wide selection of commercial, engineering and clinical purposes of the rising concepts. Researchers from academia and current their unique paintings and alternate rules, details, options and functions within the box of complex Computing and conversation Technology.
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Extra resources for Advanced Computing and Communication Technologies: Proceedings of the 9th ICACCT, 2015
Encapsulating user needs into a small area and enhancing the speciﬁcation of today’s requirement is really a challenging task for System on chip designer. This review presents the practical view of Hardware/Software co-design and its main design issues tackled in recent years. The role of SOC cannot be limited to a single task, since it is an ocean of streams like Computer Architecture, VLSI and Embedded System, which has been joined together to deal with a current multi-tasking environment. The key motive of this survey is to cover the design issues faced by SOC designer and applying all these in Hardware Software co-design.
K. C. Lobo Fig. 17 Process to be followed to calculate SNM References 1. : Digital Integrated Circuits: A Design Perspective. PHI Learning, 2nd edn. ISBN-10: 8120322576 (2003) 2. : Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J. Solid State Circuits 41(7), 1673–1679 (2006) 3. : Low-power cache design using 7T SRAM cell. IEEE Trans. -II. Express Briefs 54(4), 318–322 (2007) 4. : A novel 7T SRAM cell design for reducing leakage power and improved stability. In: International Conference on Advanced Communication Control and Computing Technologies (ICACCCT-2014), pp.
7). These transistors also help to reduce the leakage current. The other architecture is same as that of 6T SRAM cell. During read operation when Qbar is ‘0’, M5 tries to pull the node to a non-zero value and there is a chance of writing in the cell instead of reading which is known as “read upset”. To overcome this problem, 8T SRAM cell has separate bit and word lines to have a better control over read and write operations (RBL, RWL for read and WL, BL, BLbar for write) (Fig. 7). The architecture of 8T SRAM cell improves the stability and provides a read upset free operation over 6T SRAM cell [5, 6].